Research

A model can run successfully while producing wrong outputs because of hardware faults. I developed optimization methods to search for inputs that expose those failures, balancing fault coverage with test-set compactness.

ATPG-EA uses evolution strategies and includes experiments with bit flips, weight perturbations, and stuck-at faults across neural-network architectures. The repository contains the search code, experimental scripts, and workflow documentation.

Compact Functional Test Pattern Generation for DNNs Using Evolution Strategies.

Printed devices vary, and sensor signals are noisy. ADAPT-pNC brings both into training by combining second-order learnable filters, sensor augmentation, and a printed neural-network model.

I evaluated the method on 15 time-series benchmark datasets. The release includes model definitions, augmentation settings, training scripts, and evaluation notebooks.

ADAPT-pNC: Mitigating Device Variability and Sensor Noise in Printed Neuromorphic Circuits with SO Adaptive Learnable Filters.

My master’s research covered 3D CT preprocessing, organ-at-risk segmentation, and transformer-based dose prediction for head-and-neck radiotherapy. The cascade uses predicted organ segmentations, CT images, and target information to estimate a 3D dose map.

The implementation includes OAR-TRANSEG and DOSE-PYFER, with segmentation and dose-prediction models, training modules, and architecture figures.

A Cascade Transformer-Based Model for 3D Dose Distribution Prediction in Head and Neck Cancer Radiotherapy.

Device-level defects create a large fault space. This work groups faults with similar transfer functions and optimizes test inputs to increase the differences between healthy and faulty circuit responses.

The public release includes fault-injection models, clustering code, SPICE simulation scripts, and notebooks for test generation and analysis.

Automatic Test Pattern Generation for Printed Neuromorphic Circuits.

Predictive accuracy is only part of the design objective when a circuit must meet a power budget. My work develops learning methods that account for this constraint during training.

The repository provides power-aware printed-network models, constrained training routines, and experiment code.

Power-Constrained Printed Neuromorphic Hardware Training.

Robust circuit components have a cost. In this collaborative work, fault-aware training uses differentiable selection to combine normal and fault-tolerant activation functions, balancing accuracy, reliability, and resources.

The release includes the mix-and-match model, an experiment entry point, and configuration options for fault ratios and activation types.

PRINT-SAFE: PRINTed ultra-low-cost electronic X-Design with Scalable Adaptive Fault Endurance.